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Silicon Labs /MGM240PB32VNN /VDAC1_S /OUTCTRL

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Interpret as OUTCTRL

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/VDAC0_S/OUTCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MAINOUTENCH0)MAINOUTENCH0 0 (MAINOUTENCH1)MAINOUTENCH1 0 (AUXOUTENCH0)AUXOUTENCH0 0 (AUXOUTENCH1)AUXOUTENCH1 0 (SHORTCH0)SHORTCH0 0 (SHORTCH1)SHORTCH1 0 (NONE)ABUSPORTSELCH0 0ABUSPINSELCH0 0 (NONE)ABUSPORTSELCH1 0ABUSPINSELCH1

ABUSPORTSELCH0=NONE, ABUSPORTSELCH1=NONE

Description

No Description

Fields

MAINOUTENCH0

CH0 Main Output Enable
MAINOUTENCH1

CH1 Main Output Enable
AUXOUTENCH0

CH0 Alternative Output Enable
AUXOUTENCH1

CH1 Alternative Output Enable
SHORTCH0

CH1 Main and Alternative Output Short
SHORTCH1

CH0 Main and Alternative Output Short
ABUSPORTSELCH0

CH0 ABUS Port Select

0 (NONE): No GPIO Selected for CH0 ABUS Output

1 (PORTA): Port A Selected

2 (PORTB): Port B Selected

3 (PORTC): Port C Selected

4 (PORTD): Port D Selected
ABUSPINSELCH0

CH0 ABUS Pin Select
ABUSPORTSELCH1

CH1 ABUS Port Select

0 (NONE): No GPIO Selected for CH1 ABUS Output

1 (PORTA): Port A Selected

2 (PORTB): Port B Selected

3 (PORTC): Port C Selected

4 (PORTD): Port D Selected
ABUSPINSELCH1

CH1 ABUS Pin Select

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data